SSCS Distinguished Lecturer Program

Kerry Bernstein IBM T.J. Watson Research Center 1101 Kitchawan Rd, Office 26-218 Route 134 / P.O. Box 218 Yorktown Heights, NY 10598 (914) 945-1684 kbernste@us.ibm.com	--- Topic: On the Rise of an Electronic Species The human brain is vastly more complex that our best supercomputers; yet it can be argued that both systems evolve towards common underlying solutions to fundamental compute problems. Biologically-inspired electronic technologies already are enabling new products, and inversely, neuro-electronics is providing elegant tools which equip the life sciences. Perhaps, some day, machines may indeed become organically intelligent, or humans electronically supplemented. In the mean time, this new “electronic species” continues to capture more and more human capability, and gives us a lot to think about. This talk will include a number of movie clips capturing some of the capabilities of artificially intelligent machines. It will be a wild, interdisciplinary ride for future engineers. --- Topic: The Emergence of 3D Integration Technology Despite generation on generation of scaling, computer chips have remained essentially 2-dimensional. Improvements in on-chip wire delay, and in the total number of inputs and outputs have not been able to keep up with improvements to the transistor, and its getting harder and harder to hide it! 3D chip technologies come in a number of flavors, but are receiving lots of attention lately as a means of extending CMOS performance. Designing for three dimensions, however, forces us to look at formerly-two-dimensional integration issues quite differently. IBM as well as other companies and research institutions are developing ways of addressing these challenges. This timely talk follows the announcement a couple weeks ago from IBM noting our development of this breakthrough technology and its appearance on IBM’s technology roadmap. This talk will introduce 3D concepts and their architectural value, and will offer a number of movies and animations showcasing some of the capabilities that 3D-enabled computing may offer in the future. --- Topic: Caution Flag Out: Microarchitecture's Race for Power Performance Microarchitecture and technology scaling have historically shared responsibility for the microprocessor’s phenomenal generation-over-generation performance improvement. The era marked by lavish use of successively scaled, leakier MOSFETs to achieve incremental architectural transaction rate growth is coming to a close, however. Increased pipeline depth has caused supra-linear latch density expansion; shorter FO4-equivalent cycles have made control logic substantially more complex. The resulting energy per operation, scaled-process-induced delay variation, and erosion in die area access latency have become real-world constraints. This talk will explore how features of past technologies have influenced high speed microarchitectures, and how the characteristics of proposed new devices and interconnects for lithographies beyond 90nm may shape future machine design. Given our industry’s power-restricted ability to continue scaling, and the approach of fundamental, quantum-mechanical boundaries, the role of microarchitecture in extending CMOS performance will be more important than ever.
Dennis Fischette Advanced Micro Devices (AMD), Sunnyvale, CA dennis@delroy.com	--- Topic: Introduction to PLL --- Topic: DL Design for Digital Systems
Ian Galton Department of Electrical and Computer Engineering University of California, San Diego 9500 Gilman Drive La Jolla, California 92092-0407 galton@ece.ucsd.edu	--- Topic: High-Performance Pipelined ADCs --- Topic: Introduction to Fractional-N PLLs --- Topic: Performance Enhancement Techniques for Fractional-N PLLs --- Topic: Introduction to Pipelined ADCs --- Topic: Digital Background Calibration in Pipelined ADCs --- Topic:Mismatch-Shaping Techniques for Delta-Sigma Data Converters --- Topic: Understanding and Using Power Spectral Densities for Data Converter Simulation, Test, and Debug
Ali Hajimiri Moore MC 136-93 Calif Institute of Technology Pasadena, CA 91125-0001 hajimiri@CALTECH.EDU	--- Topic: Millimeter Wave
Dr. Kiyoo Itoh Fellow IEEE, and Fellow Hitachi, Ltd. Hitachi, Ltd., Central Research Laboratory 1-280, Higashi-koigakubo Kokubunji-shi, Tokyo 185-8601, Japan +81-42-323-1111(Tel) +81-42-327-7699(Fax) k-itoh@crl.hitachi.co.jp	--- Topic: Basics of RAM design and technology --- Topic: DRAM circuits --- Topic: High S/N DRAM design and technology --- Topic: RAM array design (Noise-generation/suppression) --- Topic: Low-voltage/low-power RAM circuits --- Topic: Subthreshold-current reduction circuits --- Topic: On-chip voltage conversion for RAMs
Dr. Takayuki Kawahara Chief Researcher Central Research Laboratory, Hitachi Ltd. 1-280 Higashi-Koigakubo Kokubunji Tokyo 185-8601, Japan Tel.: 81-42-323-1111 (ext.3740) Fax: 81-42-327-7774 takayuki.kawahara.rc@hitachi.com	--- Topic:Spin-transfer torque RAM (SPRAM) design and its impact on digital systems TMR (tunneling magneto resistance) devices Memory cell design SPRAM chip design Applications Emerging memory comparison --- Topic:Issues and solutions for low-voltage/low-power RAMs SRAM DRAM Other RAM *Periphery
Dr. Rudolf Koch Infineon Technologies AG Am Campeon 1-12, D-85579 Neubiberg, Germany Fax: +49-89-234 955 3574	--- Topic: Sigma-Delta A-to-D Converters Classical Nyquist-type Analog-to-Digital converters rely on the matching and precision of many hundred or thousand elements – usually resistors or capacitors. These elements do not scale well with process shrink, and, even worse, in modern deep submicron technologies they may not even be available as explicit element. Oversampled converters, in their most popular form Sigma-Delta-Converters, trade precision versus speed and are thus much better suited for modern semiconductor technologies. Most audio, speech and communications applications are based on these converters. However, they are very different from classical converters, not easy to understand for the beginner, and show sometimes strange unexpected effects severly degrading resolution or even caising instability. This talk gives a basic description of Sigma-Delta- Converter principles, properties and applications for non-experts. --- Topic: The Revival of the Continuous Time Sigma-Delta A-to-D Converter Sigma-Delta-Converters are the workhorse of modern communications circuits. In most mobile phones are several, up to a dozen, of these Analog-to-Digital Converters. The very first SDMs were continuous time implementations using well known resistor-capacitor-concepts. Then for more then a decade practically only discrete time, switched-capacitor implementations were in use, whereas during the last two years continuous time solutions came back with vengeance. This talk discusses the pros and cons of both architectures and explains why modern communication systems triggered the comeback of the old concepts. --- Topic: Modern mobile phones are rather mobile multimedia platforms than phones, combining many applications, standards, frequency ranges in one small device. The cost and power efficient implementation of all these features has significant impact on chip architecture and circuit concepts. Software defined radio concepts are under investigation for the digital baseband. The wireless transceiver, however, shows much less flexibility today. This talk discusses the challenges of these ‘all-in-one’ phones and their impact on circuit concepts, with emphasis on the data converters.
Prof. Tadahiro Kuroda Keio University 3-14-1, Hiyoshi, Kohoku-ku Yokohama 223-8522, Japan +81-45-566-1534 (Phone&FAX) kuroda@elec.keio.ac.jp http://www.kuroda.elec.keio.ac.jp	--- Topic: Low Power CMOS Design Abstract: This talk will discuss circuit techniques and design methodologies for low-power and high-performance CMOS LSI. Ten tips as good practice in low power CMOS design will be discussed from device to circuit, design automation, and system. Quantitative analysis as well as the latest design examples will be presented. --- *Topic:* Challenges and Opportunities in System LSI Abstract: Scaling of CMOS integrated circuits is becoming difficult, due mainly to rapid increase in power dissipation and device variations. How will the semiconductor technology and industry develop? This presentation will discuss challenges and opportunities in system LSI from three levels of perspectives: transistor level (physics), IC level (electronics), and business level (economics). --- *Topic:* CMOS Proximity Wireless Communications Abstract: Performance gap between computation in a chip and communication between chips is widening. Electrical non-contact interfaces using inductive/capacitive coupling have advantages over mechanical interfaces employing Through Silicon Vias and micro bumps. In this talk, CMOS proximity wireless communications for SiP integration will be discussed in various levels from signaling, circuit, layout, and magnetic field design.
Prof. Thomas Lee Center for Integrated Systems, CIS-205 420 Via Palou Mall Stanford University Stanford, CA 94305-4070 +1 650 725 3709 (Tel) +1 650 725 3383 (Fax) tomlee@ee.stanford.edu	--- Topic: History of Radio --- Topic: CMOS RF Integrated Circuit Design: Low-noise amplifiers RF-quality passive components in standard digital CMOS Phase noise in oscillators Phase-locked loops for clock generation, clock recovery, and frequency synthesis Transceiver architectures
Prof. John R. Long Deft University of Technology johnlong@cobalt.et.tudeft.nl	--- Topic: Wireless IC Building Blocks in CMOS/BiCMOS
Dr. Kofi Makinwa Associate Professor Electronic Instrumentation Lab Delft University of Technology Mekelweg 4, 2628CD Delft The Netherlands +31 15 27 86466 (Tel) +31 15 27 85755 (Fax) E k.a.a.makinwa@tudelft.nl k.a.a.makinwa@tudelft.nl ei.ewi.tudelft.nl/	--- Topic: CMOS Temperature Sensors CMOS temperature sensors have a wide range of applications: thermal management of CPUs and SOCs, refresh-rate control in DRAMs and temperature compensation of MEMS oscillators. However, achieving sufficient accuracy in the face of typical CMOS “issues” such as 1/f noise, component mismatch and process spread is quite challenging. This talk will discuss how temperature sensors with inaccuracies of only a few tenths of a degree can be realized in standard CMOS. --- Topic: Smart CMOS Sensors A smart sensor consists of a sensor and its interface electronics in the same package. Due to the low-level output of most sensors, designing interface electronics that “does no harm,” is quite challenging, especially in CMOS processes, whose precision is limited by 1/f noise and component mismatch. This talk will discuss the use of dynamic techniques such as dynamic element matching, switched-capacitor filtering and sigma-delta modulation in the design and realization of state-of-the-art smart CMOS sensors. --- Topic: Dynamic Offset Cancellation Techniques in CMOS In CMOS circuits, offset is a fact of life! Even in modern processes, device mismatch typically results in several millivolts of offset. But many analog circuits, e.g. precision amplifiers, sensor interfaces and ADCs, require much lower offset levels. This talk will discuss the use of dynamic offset cancellation techniques such as auto-zeroing and chopping to routinely achieve microvolt levels of offset in standard CMOS.
Toshiaki Masuhara Executive Director, MIRAI Project Association of Super-Advanced Electronics Technologies(ASET) AIST Tsukuba West 7, 16-1 Onogawa, Tsukuba Ibaraki, 305-8569 JAPAN t-masuhara@mirai.aist.go.jp	--- Topic: Devices/Circuits for Low Power SoC
Akira Matsuzawa Tokyo Institute of Technology S3-27, 2-12-1, 0-Okayama Meguroku, Tokyo 152-3552, JAPAN akira-matsu@u01.gate01.com	--- Topic: Mixed signal technologies
K. Nagaraj Texas Instruments nagaraj@ti.com	--- Topics: Forthcoming.
Sreedhar Natarajan CEO, Emerging Memory Technologies, Inc. sn@ieee.org	--- Topic: Low-Power Memory Design for 65nm
Bram Nauta IC-Design Chair University of Twente P.O. Box 217 7500 AE Enschede The Netherlands B.Nauta@utwente.nl	--- Topic: Analog CMOS circuits for transceivers
Clark. T. C. Nguyen UC-Berkeley ctnguyen@eecs.berkeley.edu	--- Topic: RF MEMS
Prof. Vojin G. Oklobdzija ACSEL Laboratory Department of Electrical and Computer Engineering University of California Davis, CA 95616 U.S.A. (510) 486-8171 (Tel.) alternate (530) 752-5634 (510) 486-0790 Fax vojin.ucdavis@gmail.com	---Topic: Timing and Clocking, Clocked Storage Elements in High-Performance and Low-Power Processors: t iming issues and design guidelines, "time-borrowing," clock skew tolerance. ---Topic: VLSI Arithmetic: Circuits for arithmetic operations, "critical path" optimization, implementation and algorithms. ---Topic: Modern Microprocessor Architectures: From RISC to Super-Scalar: principles, relation to micro-architecture and pipeline, high-performance implementation, super-scalar pipeline. ---Topic: Low-Power Design Techniques: logic, technology and circuits, logic design style, pipelining and voltage scaling.
Dr. Betty Prince Memory Strategies International 16900 Stockton Drive Leander TX 78641 USA bprince@memorystrategies.com	--- Topic: Trends in Solar Energy Technology - Solar polysilicon production technology, and current and emerging solar cell technologies. --- Topic: Embedded Non-Volatile Memories *Abstract: Technology issues for embedded non-volatile memories and applications for chips containing these memories are discussed. Memory technologies covered include: floating gate, nitride storage, nanocrystal flash, 3-D memories and others. --- Topic: Embedded RAM Memories Abstract:* Technology issues for embedded RAM are discussed including DRAM, PSRAM, and SRAM. Future RAM technologies such as capacitorless DRAM, MIM capacitor DRAM, and vertical SRAM are covered. --- Topic: Nanotechnology and Emerging Memories *Abstract:* Scaled and emerging memory technologies and issues are discussed. These include: issues in scaling current memories such as vertical processing, future RAMs such as gain cells and negative differential conductance memories, emerging memories such as MRAM, FeRAM, PC-RAM, etc., new memory technologies such as MEMs, molecular and single electron.
Behzad Razavi UCLA Dept of EE Rm. 56-147D, ENG 4 Los Angeles, CA 90095-0001 USA (310)206-1633(Tel) (310)206-8495(Fax) razavi@icsl.ucla.edu	--- Topic:CMOS Technology Characterization for Analog and RF Design --- Topic:CMOS Wireless Transceivers for Dual-Band Applications --- Topic:High-Speed A/D Converter Design --- Topic:Frequency Synthesizer Design for Wireless Applications
Mehmet Soyuer IBM TJ Watson Res Ctr Room 37-130 PO Box 218 Yorktown Heights NY 10598-0218 soyuer@us.ibm.com	--- Topic: Monolithic phase-locked-loop designs for clock and data recovery --- Topic: clock multiplication and frequency synthesis using silicon and SiGe technologies
Jan Van der Spiegel University of Pennsylvania Dept. of Electrical Engineering/329M 200 S. 33rd Street Philadelphia PA 19104-6390 ( 215) 898 7116 (Tel) (215) 573 6045 (Fax) jan@ee.upenn.edu	--- Topic: Biologically Inspired Optical Vision Sensors: strategies of biological systems, visual sensory system, neuromorphic sensing and CMOS implementations including pre- and post-processing. --- Topic: The ENIAC - from vacuum tubes to microchip: history and operation of the first large scale electronic digital computer, reconstruction of the ENIAC in CMOS technology.
Mircea R. Stan University of Virginia mrs8n@cms.mail.virginia.edu	--- Topic: High-performance low-power VLSI --- Topic: Temperature-aware circuits and architecture --- Topic: Embedded systems --- Topic: Nanoelectronics
David Su Atheros Communications, MS: SC1-1C 5480 Great America Parkway Santa Clara, CA 95054 david.su@atheros.com	--- Topic: Introduction to CMOS RF Power Amplifier Design This talk introduces the design of CMOS RF power amplifier for digital wireless communications with emphasis on how the applications and specifications impact the power amplifier design. Challenges due to large peak-to-average ratio as well as low breakdown voltages of CMOS technology are presented. The talk concludes with a survey of linearity and efficiency enhancement techniques. --- Topic: CMOS transceiver design for 802.11 wireless LAN The widespread adoption of Wireless Local Area Networks (WLAN) based on the IEEE 802.11 standards created the demand for low-cost, highly integrated CMOS transceivers. The design and implementation of CMOS WLAN transceivers is the subject of this talk. It consists of: o an overview of the IEEE 802.11 WLAN specifications o a discussion on transceiver architectures and frequency plans o a case study of a CMOS wireless transceiver --- Topic: Challenges in designing CMOS wireless System-on-a-chip This talk describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifier, power amplifier, mixer, and frequency synthesizer. System-on-a-chip integration issues are also discussed.
Albert J. P. Theuwissen Chief Scientist , DALSA, Inc. a.j.p.theuwissen@ewi.tudelft.nl	--- Topic: Noise in solid-state Imagers: Basics and Spacemanship
Roland Thewes Infineon Roland.Thewes@qimonda.com	--- Topic: Bio-sensors --- Topic: DRAM Core Circuitry
Ken Uchida Toshiba Corporation ken1.uchida@toshiba.co.jp	--- Topic: Single-Electron Transistors and logic circuits
Werner Weber Infineon Technologies, AIM TI MU FP D-81726 Munich, Germany Office: Am Campeon 1-12 D-85579 Neubiberg, Germany +49 89 234 48470 (Tel) +49 89 234 955 7082 (Fax) werner.weber@infineon.com	--- Topic: '3D Stacking of Silicon Chips' This presentation will look into the farther future of system integration and highlight chances and possible stumbling blocks of frontend-focused 3D interconnect technologies. Initially, the achieved status of research on 3D integration is reviewed. Then, we discuss challenges on design, signal integrity, power integrity, heat dissipation and test. Different parameter sets for various products/applications are discussed and alternative integration technologies are compared which compete for best performance and lowest cost. Finally, an outlook will be given based on the running funding project 'e-CUBES', which fosters the exploitation of 3D integration technologies. --- Topic: 'Industrialization of MEMS' Micro-Electro-Mechanical Systems (MEMS) have been a research focus in academia and industry since many years. Recently several examples of successful industrializations of MEMS appeared and carried major encouragement into the research community. This presentation gives an overview on the technical concepts used today and provides information about important technical and economic trends in this field.
S. Simon Wong Center for Integrated Systems Stanford University, Stanford, CA 94305-4070 Phone : 650-725-3706 FAX : 650-725-3383 Email : wong@ee.stanford.edu	--- Topics: Forthcoming.
Ian Young Director, Advanced Circuits and Technology Integration Intel Corporation MS-RA3-256 5200 NE Elam Young Parkway Hillsboro, OR 97124-6497 ian.young@intel.com	--- Topic: Mixed-Signal RF CMOS circuits. --- Topic: Phase Locked Loops.