 Speaker: Jan Van der Spiegel (Fellow IEEE) is a Professor of the Electrical and Systems Engineering Department, and the Director of the Center for Sensor Technologies at the University of Pennsylvania. He received his Masters degree in Electro-Mechanical Engineering and his Ph.D. degree in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. His primary research interests are in high-speed, low-power analog and mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters.
Prof. Van der Spiegel is a fellow of the IEEE, the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching, and the Presidential Young Investigator Award.
He has served on several IEEE program committees (IEDM, ICCD, ISCAS and ISSCC) and is currently the technical program chair of the International Solid-State Circuit Conference (ISSCC 2007). He is an elected member of the IEEE Solid-State Circuits Society and is also the SSCS chapters Chairs coordinator and former Editor of Sensors and Actuators A for North and South America. He is a member of Phi Beta Delta and Tau Beta Pi.
Abstract: This lecture deals with a variety of optical sensors that are architecturally inspired by biological systems. A brief overview of the underlying biological mechanisms found in sensory systems will be discussed, as well as signal processing strategies and sensory circuits, with special attention given to visual systems. The talk will describe how these properties can be used to design and build neuromorphic vision sensors with pixels that contain both detectors and local signal processing elements. One such chip has been designed and fabricated for motion perception and visual tracking. It performs two-dimensional visual acquisition and tracking of moving objects. Another example is an imager for the detection of higher level image features, such as line orientations, corners, junctions (T-, X-, Y-type) and linestops. Finally, our work on a imager that is capable to extract polarization information will be discussed.
|
|
 Speaker: Massoud Pedram received a B.S. in Electrical
Engineering from California Institute
of Technology in 1986 and M.S. and Ph.D. in Electrical
Engineering and Computer Sciences from the University
of California, Berkeley in 1989 and 1991, respectively. He then joined
the Department of Electrical Engineering
- Systems at the University of Southern
California where he is currently a professor. Dr. Pedram is a recipient
of the National Science Foundation's
Young Investigator Award (1994) and the Presidential
Early Career Award for Scientists and Engineers (a.k.a. the Presidential
Faculty Fellows Award) (1996). His research has received a number of awards
including two Best Paper Awards from the International Conference on Computer
Design, two Design Automation Conference Best Paper Awards, and an IEEE
Transactions on VLSI Systems Best Paper Award.
Abstract: Multi-threshold CMOS (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low Vth transistors for logic cells and low leakage, high Vth devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the subthreshold conduction leakage currents in the sleep mode. One of the downsides of MTCMOS technique is the energy consumed during repeated transitions between the sleep and active modes of the circuit operation.
In my talk I will present a charge recycling MTCMOS technique that cuts the energy consumption for mode transitions in half while preserving the wakeup delay and reducing the ground bounce level in the target circuit. Tradeoffs related to the energy saving and leakage power increase of the charge-recycling vs. conventional MTCMOS will be discussed and related circuit optimization problems will be presented. I will conclude my talk by describing the application of the charge-recycling MTCMOS technique to row-based standard cell layouts. |
 Speaker: Dr. Prince is CEO of Memory Strategies International. She has 30 years experience in the semiconductor industry having worked with Texas Instruments, N.V. Philips and Motorola in memory technology and marketing management, at R.C.A. in the development of an early microprocessor and at Fairchild in semiconductor process technology. She is author of the books: Semiconductor Memories (1982), Semiconductor Memories 2nd Edition (1992), High Performance Memories, (1996, revised 1999) all published by John Wiley & Sons, Emerging Memories - Technologies and Trends, (2002) published by Kluwer Academic, and Modern Memories to be published by John Wiley & Sons. She is a Senior Member of the IEEE, an IEEE SSCS Distinguished Lecturer, is on the Program Committee of the IEEE Custom Integrated Circuit conference and served from 1991-1994 on the Technical Advisory Board of IEEE Spectrum magazine. She was founder of the JEDEC JC-16 Interface Standards Committee and was active for many years on the JC-42 Memory Committee where she was co-chair of the SRAM standards group. She has been U.S. representative to the IEC SC47A WG3 Memory Standards Committee. She has served on the Technical Advisory Board of several memory companies including: Cavendish Kinetics, Emerging Memory Technologies and Silicon Access Networks and was a Director of Mosaid Technologies for many years. She holds patents in the memory, processor and interface areas. She has a B.S. and M.S. in physics and math from the University of New Mexico and the University of California, an M.B.A. and a Ph.D. from the University of Texas with doctoral dissertation on fractal modelling.
Abstract: Scaled and emerging memory technologies and issues are discussed. These include for RAMs: issues in scaling current SRAM memories such as cell stability, sub-threshold leakage, and variability and solutions including high k dielectrics, vertical structures, and additional transistors in the cell; issues in scaling DRAMs including power dissipation and vertical capacitors and solutions such as SOI Trench and stacked MIM capacitors; future DRAMs including floating body cells, gain cells and negative differential conductance memories. For non-volatile memory, issues with floating gate flash cells both NAND and NOR are discussed along with the trend to trapping site storage both nitride storage and nanocrystal in the near term, emerging memories such as MRAM, FeRAM and PC-RAM longer term, and much further out new memory technologies such as MEMs, molecular and single electron.
|
 Speaker: Albert Wang received a BSEE degree from the Tsinghua University, China, in 1985 and a PhD EE degree from The State University of New York at Buffalo in 1995. He was National Semiconductor Corporation from 1995 to 1998. He joined the Department of Electrical and Computer Engineering at the Illinois Institute of Technology (IIT) in 1998, where he is currently an Associate Professor and Director for the Integrated Electronics Laboratory. His research interests focus on Analog/Mixed-Signal/RF ICs, Advanced on-Chip ESD Protection, IC CAD and Modelling, Systems-on-a-Chip (SoC), and Advanced Semiconductor Devices, etc.
Wang received the CAREER Award from the National Science Foundation in 2002. He authors the book “On-Chip ESD Protection for Integrated Circuits” (Kluwer Academic Press, 2002) and more than 110 peer-reviewed papers, and holds several U.S. patents. Wang serves as Editor for the IEEE Electron Device Letters and Associate Editor for the IEEE Transactions on Circuits and Systems I. He was Associate Editor for the IEEE Transactions on Circuits and Systems II, Guest Editor for the IEEE Journal of Solid-State Circuits and Guest Editor-in-Chief for the IEEE Transactions on Electron Devices. He has been an IEEE Distinguished Lecturer for both the Electron Devices Society and the Solid-State Circuits Society since 2001. He is currently Vice President for IEEE Electron Devices Society (EDS) and serves on the EDS ExCom and AdCom Board. He is a Member of the IEEE VLSI Technology and Circuits Committee and the IEEE Analog Signal Processing Technical Committee. Wang serves on the Wireless Committee for the SIA International Technology Roadmap for Semiconductor 2007. He has been serving on various posts for many IEEE conferences, e.g., CICC, RFIC, APC-CAS, ASP-DAC, ICSICT, ISCAS, IPFA, ICEMAC, NewCAS, ISTC, IRPS, ASICON, AP-RASC, MAPE, EDSSC, MIEL and IEDST etc. He is a Board Director for the North American Chinese Semiconductor Association. He is a frequent speaker at various industrial/academic/international forums and a frequent consultant to the IC industry.
Abstract: ESD (Electro-Static Discharge) failure becomes a major IC reliability problem as semiconductor IC technologies continues migrate into the VDSM (very-deep-sub-micron) regime. On-chip ESD protection circuitry design emerges as a grand challenge to RF/mixed-signal IC designs recently. Yet traditional trial-and-error approaches still dominate in ESD design practices, which become increasingly unacceptable to RF/MS IC designs. This lecture discusses various key aspects for ESD protection design including ESD protection principles, mixed-mode ESD design method, RF ESD design evaluation and ESD design prediction, etc. Practical ESD protection circuit design examples will be presented. |
