Implications of Near-Limit CMOS on Circuits and Applications Workshop

Implications of Near-Limit CMOS on Circuits and Applications Workshop
13 February 2003 -- after the ISSCC at San Fracisco Marriott

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While technologists continue to provide us with ever-faster CMOS devices, it is clear that these fast devices have properties that were not seen in CMOS just a few years ago. From the perspective of circuits and applications, these unexpected properties are mostly detrimental, resulting in increasing challenges to circuits and systems designers. From the technologists' perspective, we are approaching the limits of scdaled CMOS. Scalling degraded device chararacteristics challenging the circuits designer. This workshop provided an open forum for discussions of the inplications of evolving CMOS, near its limits, on circuits and applications. Invited speakers lead off disscussions related to:

CMOS near its scaling limits, status and future prospects
Power and power density, issues at the chip and system levels
Reliability, issues such as burn-in, soft error, error correction, etc.
gate current, ists limits and effects on circuits.
Low-power designs, their benefits and potential pitfalls

Organizers: Tak Ning, IBM Research, Stan Schuster, IBM research

Topic		Speaker
Challenges Near the Limits of CMOS Scaling		Yuan Yaur, Univeristy of California
Low-Power Technologies in the Near-Limit CMOS Regime		Kazuo Yano, Hitachi
Infant-Mortality Control by Burn-In and by Design		Shirley Glenn, Intel
Transistor and BEOL Tradeoffs in Near-Limit CMOS Technology		Rich Klein, Advanced Micro Devices
Effects of Gate Tunnelling in Near-Limit CMOS Circuits		Hisham Massoud, Duke University
Low-Power Challenges for Digital CMOS Beyond 90nm		Shekhar Borkar, Intel
Design, Process and Environmental Contributors to Delay Variation		Kerry Bernstein, IBM
Untitled		Rob Rutenbar, Carnegie Mellon University