In this workshop for microprocessor design experts discussed technical
directions that designers are exploring to achieve high-performance microprocessors
at multi-GHz frequencies in the 0.1um process generation. The workshop
provided opportunities for participants to interact. The workshop was
held on the day preceding ISSCC 2000 and lasted the entire day. Attendance
was limited and pre-registration was required.
|
Topic
|
|
Speaker
|
|
Introductions/Processor Design Challenges
|
|
Ian Young, Intel
|
|
Technology Trends and their Implications for
Interconnect Delay (0.18 microns to 0.05 microns)
|
|
Mark Horowitz, Stanford
|
|
Interconnect Analysis of High-Frequency Effects
|
|
Larry Pilleggi, CMU
|
|
Clock Networks and Power Delivery
|
|
Phillip Restle, IBM
|
|
Glovally Asyn., Locally Design Techniques
|
|
Kenneth Yun, UC San Diego
|
|
Interconnect Circuit Design Techniques
|
|
San Naffziger, HP
|
|
Logis Circuit Families
|
|
Undeclared
|
|
Clocked Storage Elements
|
|
Hamid Partovi, AMD
|
|
Skew-Tolerant Circuit Design
|
|
David Harris, Harvey Mudd
|
|
Design Methodology and CAD Tools
|
|
Shantanu Ganguly, Intel
|
|
Processor Architechture Directions for GHz Processors
|
|
Jim Smith, Univ. of Wisconsin
|
|
CPU Memory Hierachy and Processor I/O
|
|
Undeclared, Intel
|
|
Workshop Discussion and Summary
|
|
Ian Young, Intel
|
Organizer: Ian Young, Intel
Arrangements by: Suzanne Demarie, Courtesy Associates |
