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Internal Cool Electronics (ICE)
Workshop |
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| To Past Workshops Page |
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Topic
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Speaker
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A Scaling Scenario for Ultra-Small CMOS with Temperature
as a Parameter
|
R.H. Dennard, IBM T.J. Watson Research Center
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DARPA Optimization in Cold CMOS Technology
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M. Nisenoff, Naval Research Laboratory |
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Device Optimization and Performance Projection of Cooled
CMOS
|
Y. Taur, IBM T.J. Watson Research Center |
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Low temperature 50 nm - 100 nm MOSFET Design for Room Temperature Testing
|
K. Jackson, A. Lochtefeld, and D.A. Antoniadis, MIT |
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CMOS Processor Design at Low Temperatures
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E. Anderson, Commercial Data Servers |
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SiGe BiCMOS Circuit Technology for Cryogenic Applications
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J. Cressler, Auburn University
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Hybrid Josephson-CMOS Technology at Low Temperatures
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T. Van Duzer, University of California, Berkeley
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Cryo Computing at -40 degree C with Low Cost Proven
Technology
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J. Peeples, Kryotech Corporation |
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Cryogenic Cooling of Advanced Device & System
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P. Halder and E. Moser, Intermagnetics General |
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Thermionic Coolers Using lll-V Materials
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C. LaBounty, A. Shakouri and J. Bowers, University of California, Santa Barbara |
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Electronic Microcoolers
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U. Ghoshal, IBM Austin Research Laboratory |
