Best Papers in the
Journal of Solid-State Circuits

The annual award to recognize the best paper published in the IEEE Journal of Solid-State Circuits is judged on the basis of outstanding achievement, significance, clarity of presentation, timeliness. The prize consists of a $1,000 and a certificate presented to the authors at the ISSCC.

Most frequently downloaded recent articles -- Classic top cited articles -- Tutorials

Alireza Shirvani, Daavid K. Su, and Bruce A. Wooley
A CMOS RF power amplifier with parallel amplification for efficient power control
Volume: 37 , Issue: 6 , June 2002
Pages:684 - 693

Marko Sokolich, Charles H.Fields, Stephen Thomas III, Binqiang Shi, Young Kim Boegeman, Mary Montes, Rosanna Martinez, Allan R. Kramer, and Meena Madhav
A low-power 72.8-GHz Static Frequency Divider in AlInAs/InGaAs HBT Technology
vol. 36, pp. 1328 - 1333, September 2001

Ichiro Fujimori, Akihiko Nogi, and Tetsuro Sugimoto
A Multibit Delta–Sigma Audio DAC with 120-dB Dynamic Range
vol. 35, pp. 1066 - 1073, August 2000.

1999
pdf of paper

Brian P. Brandt and Joseph Lutsky
A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist
vol. 34, pp. 1788 - 1795, December 1999.
Mark. J. Loinaz, K. J. Singh, Andrew. J. Blanksby, David A. Inglis, Kamran. Azadet, and Brain Ackland
A 200-mW, 3.3-V, CMOS Color Camera IC Producing 352 × 288 24-b Video at 30 Frames/s
vol. 33, pp. 2092 - 2103, December 1998.
1997
Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, and Stephen W. Harston
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
vol. 32, pp. 1896 - 1906, December 1997.

1996
pdf of paper

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John M. Drynan, MasahirKomuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko Ichinose, Tomoo Imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, and Takashi Okuda
A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay
vol. 31, pp. 1656- 1668, November 1996

1995
pdf of paper

Lake Kun Tan and Henry Samueli
A 200 Mhz Quadrature Digital Synthesizer/Mixer in 0.8 mm C.M.O.S.
vol. 30, pp. 193-200, March 1995

1993

Michiel de Wit. Khen-San Tan. and Richard K. Hester
A Low-Power 12b Analog-to-Digital Converter with On-Chip Precision Trimming
vol. 28, pp. 455 - 461, April 1993

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